1. Field of the Invention
The present invention relates to a method of forming a pattern in the manufacturing of a semiconductor device. More particularly, the present invention relates to a method of using photoresist to form an electronics pattern of a semiconductor device.
2. Description of the Related Art
When manufacturing a DRAM, in order to minimize gate resistance and attain the optimum refresh time it is necessary to selectively silicidate the gates. In this case, the silicide layer should not be formed on the active area.
Lately, a merged DRAM with logic (MDL) has been recognized for its high performance and small chip size. When manufacturing an MDL, silicide is formed on both an active area and on gates, or on parts of the active area and gates in a peripheral circuit and logic portion of the MDL, in order to reduce contact resistance or sheet resistance of the gates and source/drain. On the other hand, the silicide is selectively formed on the gates of a memory cell array portion in order to attain the optimum refresh time.
In the case of manufacturing a SRAM, suicide is selectively formed on the active area and on all of the gates in order to attain a high-speed operation.
In the case of an NVM, the greater the pattern density, the longer the gate must be. Therefore, silicide has only recently begun being selectively formed on the gates of NVMs in order to reduce resistance.
Techniques of silicidating a selected area in the manufacturing of a semiconductor device is disclosed in Korean Patent Laid-Open Publication No. 2000-000885 and Japanese Patent Laid-Open Publication No. Hei 11-163326.
The technique disclosed in Korean Patent Laid-Open Publication No. 2000-000885 will be described with reference to the flow chart of FIG. 1 and the sectional views of FIGS. 2 through 8.
First, a plurality of gates 12 including side wall spacers 11 are formed on a substrate 10. Then, a target layer to be patterned, for example, a silicidation blocking dielectric layer 14, is formed over the entire surface of the substrate 10, and an anti-reflection layer 16 is formed on the silicidation blocking dielectric layer 14 (step 1), as shown in FIG. 2. Next, in step 2, a photoresist coating 20 is formed on the anti-reflection layer 16, as shown in FIG. 3. In step 3 and as shown in FIG. 4, an exposure process is performed using a mask 30 having a transmission area corresponding to an upper portion of the gates 12 that are to be subjected to silicidation. In step 4 and as shown in FIG. 5, the exposed portion of the photoresist 20 is removed using a general developing solution, whereby a photoresist pattern 20P is formed. The photoresist pattern 20P exposes areas directly above the gates 12. In step 5, portions of the anti-reflection layer 16 and the silicidation blocking dielectric layer 14 are removed using the photoresist pattern 20P as an etching mask, whereupon the upper portions of the gates 12 are exposed as shown in FIG. 6. Then, in step 6, the photoresist pattern 20P and the remainder of the anti-reflection layer 16 are removed, as shown in FIG. 7. Finally, in step 7, a silicidation process is performed in which a silicide layer 40 is formed on the upper portion of the gates 12, as shown in FIG. 8.
However, this prior art process is complicated because it requires the forming of the anti-reflection layer 16 to prevent irregular reflection at the surface of the silicidation blocking dielectric layer 14, and the removing of the anti-reflection layer 16 after the patterning process. Also, the smaller the gates 12 and the greater their density, the more likely a misalignment error will occur during the exposure process. When such a misalignment error occurs, the silicide layer is not formed locally on the upper portion of the gates 12 or an undesirable silicide layer is formed locally on an active area.
Also, according to the prior art method disclosed in Korean Patent Laid-Open Publication No. 2000-000885, the entire surface of the substrate is coated with undoped silicate glass (USG). Subsequently, the USG layer is etched back using a microloading effect. As a result, the USG layer remains in the memory cell array portion where the gate patterns are dense, whereas the USG layer is almost etched in the peripheral circuit and logic portion where gate patterns are sparse. However, when the USG layer is etched back, the remaining USG layer is not uniform, and the selectivity of the process to an etch-back stopper of a lower portion of the USG layer and the silicidation blocking dielectric layer is low. Therefore, the process is marked by poor stability and reproducibility. Also, it becomes impossible to achieve partial silicidation of the peripheral circuit and logic portion.
Japanese Patent Laid-Open Publication No. Hei 11-163326 discloses methods of forming a semiconductor device having a memory cell array portion (region A) and a logic portion (region B). In one embodiment, as shown in FIG. 9, a silicidation blocking dielectric layer 14 and photoresist 20 are sequentially formed over the entire surface of a substrate 10 on which gates 12 and gate side wall spacers 11 have been formed. Next, as shown in FIG. 10, the photoresist 20 in the peripheral circuit and logic portion (region B) is exposed using a mask 35. The exposed photoresist 20 is developed to form a photoresist pattern 20P that covers the memory cell array portion (region A) and exposes the peripheral circuit and logic portion (region B), as shown in FIG. 11. The photoresist pattern 20P is etched back to form a secondary photoresist pattern 20Pxe2x80x2 that exposes an upper portion of gate patterns in the memory cell array portion (region A), as shown in FIG. 12. Next, the blocking dielectric layer 14 is etched using the secondary photoresist pattern 20Pxe2x80x2 as an etching mask to form a blocking dielectric layer pattern 14P. At this stage of the method, an active area of the peripheral circuit and logic portion (region B) and an upper portion of gates 12 in the memory cell array portion (region A) are exposed, as shown in FIG. 13. Subsequently, the secondary photoresist pattern 20Pxe2x80x2 is removed, as shown in FIG. 14, and a silicidation process is performed such that a silicide layer 40 is formed on the upper portion of the gates 12 in the memory cell array portion (region A), on the upper portion of the gates 12 in the peripheral circuit and logic portion (region B), and on the active area of the peripheral circuit and logic portion (region B), as shown in FIG. 15.
However, this method is also complicated because of the numerous steps required, including the steps of forming a silicidation blocking dielectric layer, forming a photoresist layer, exposing the photoresist layer, developing the photoresist layer (forming a photoresist pattern), etching back the photoresist pattern, etching the blocking dielectric layer, removing the photoresist pattern, and performing silicidation. Also, it is difficult to provide a high degree of selectivity in the etch back of the photoresist pattern with respect to the blocking dielectric layer. In the case of low selectivity, the upper portion of the gates are exposed. Moreover, the etch-back process does not produce a high degree of uniformity.
Therefore, an object of the present invention is to overcome the disadvantages and limitations of the prior art.
More specifically, one object of the present invention is to provide a relatively simple method of forming a pattern in the manufacturing of a semiconductor device, which is not limited by the design rule of the device.
Another object of the present invention is to provide a relatively simple silicidation method which facilitates the selective silicidation of an area(s) on a substrate and that is economical to carry out.
It is yet another object of the present invention to provide a method of forming a photoresist pattern without using an exposure process, thereby obviating the misalignment errors that would otherwise become more likely to occur the smaller the design rule becomes.
The method of forming a pattern without using an exposure process comprises steps of forming a target layer to be patterned on a substrate having a pattern that defines a step, forming a photoresist layer on the target layer, forming a photoresist pattern by treating the photoresist layer with a developing solution to thereby form a photoresist pattern having a height smaller than that of the step, removing the target layer exposed by the photoresist pattern to thereby form a predetermined pattern, and removing the photoresist pattern.
The treating of the photoresist layer with the developing solution is preferably carried out until the height of the photoresist pattern is preferably 20-90% of the height of the step.
The photoresist layer is preferably formed of photoresist including a first novolak resin and a photoactive compound of 3-15 wt % based on the total weight of the first novolak resin, photoresist including a first novolak resin, a second novolak resin of 10-60 wt % based on the total weight of the first novolak resin and having a rate of dissolution in the developing solution of 300-1500 xc3x85/sec, and a photoactive compound of 15-30 wt % based on the total weight of the first novolak resin, or photoresist including a first novolak resin, polyhydroxystyrene of 10-60 wt % based on the total weight of the first novolak resin, and a photoactive compound of 15-30 wt % based on the total weight of the first novolak resin.
Preferably, the substrate on which the photoresist layer has been formed is baked before the developing step.
The photoresist layer may also be formed of photoresist including a polymer, in which a t-butyloxycarbonyl group and an acetal group are combined with a backbone of the polymer as a protecting group, and a photoacid generator of 0.5-8 wt % based on the total weight of the polymer. in this case, the baking of the substrate preferably comprises first baking the substrate at a temperature of 90-120xc2x0 C. for 30-120 seconds, and secondly baking the substrate at a temperature of 130-160xc2x0 C. for 30-120 seconds.
The silicidation process for selectively silicidating an area(s) on a substrate incorporates the method of forming a pattern.
Specifically, the silicidation process of the present invention is particularly well-suited to the manufacturing of MDLs in which the substrate has a memory portion and a peripheral circuit and logic portion at the periphery of the memory portion.
In this case, a target layer, as a silicidation blocking layer, is formed on the gate patterns of the peripheral circuit and logic portion and the memory portion of the substrate. A photoresist layer is formed on the target layer at both the memory portion and peripheral circuit and logic portion of the substrate such that the upper surface of the photoresist layer is situated above the target layer.
Then, only photoresist that is located at the peripheral circuit and logic portion is exposed.
Next, a portion of the photoresist layer located over a first area at the memory portion of the substrate is dissolved, and all of the photoresist layer that has been exposed at the peripheral circuit and logic region is dissolved, by soaking the photoresist layer in a developing solution. The resulting photoresist pattern exposes part of the target layer at the memory portion and exposes at least part of the target layer on both the gate pattern and an active area of the peripheral circuit and logic portion.
Next, the exposed parts of the target layer at both the memory portion and peripheral circuit and logic portion of the substrate are removed, followed by the removal of the photoresist pattern. Subsequently a silicide layer is formed on the upper portion of the gate pattern of the memory portion, and in an active area and on the upper portion of the gate pattern of the peripheral circuit and logic portion of the substrate.